This invention relates to the field of semiconductor wafer processing, and to a strengthened-wafer reduction of breakage mishaps in the testing and handling of thinned and brittle wafers of, for example, the gallium arsenide microwave integrated circuit type.
The electrical properties of some semiconductor wafer materials, notably gallium arsenide and combinations of other materials with gallium arsenide, require wafer circuit die thicknesses that are in the range of 100 micrometers (100 .mu.m). In fabricating integrated circuit versions of the well-known "Stripline.RTM." electrical transmission line, for example, it is found that desirable values of transmission line characteristic impedance plus conductor physical size and separation dictates that transmission line conductor members be located only 100 .mu.m or less thickness of gallium arsenide material away from a conductive ground plane member.
Insofar as electrical properties of the resulting circuits are concerned, this 100 .mu.m thickness dimension is therefore readily acceptable. In fact, the only major difficulty with such thin wafers and circuit die is the considerable wafer fragility and handling difficulties introduced by such thicknesses (a human hair is about 60 .mu.m in diameter, the thickness of a piece of paper is about 150 .mu.m). The necessity of handling wafers and the circuit die removed therefrom numerous times prior to their mounting in an integrated circuit package is well known in the integrated circuit art. One especially difficult portion of this handling occurs during the probe testing of fully fabricated wafers--before the host wafer is scribed and broken or otherwise divided into individual circuit die members.
Preferably such probe testing is accomplished while a full sized fabricated wafer of two-inch diameter, for example, is held on the faceplate of a vacuum chuck member. Here it is subjected to individual circuit testing by way of probe fingers that are dropped onto connecting pads of the completed circuit. Clearly the steps of presenting a fully fabricated thin and brittle gallium arsenide wafer in this posture and the physical stresses of receiving multiple probe fingers in numerous different locations across the face of the wafer, is attended by an undesirable degree of breakage hazard.
In the past, this breakage hazard has been met by a backside mounting of completed wafers onto a carrier member such as a piece of glass or on a more rugged semiconductor wafer--such as a silicon wafer of normal thickness. Usually this mounting is accomplished with the aid of a temporary attachment material such as low melting temperature wax with the wafer being removed from such protective attachment by heating following the probe testing operation. Clearly the cost and complexity of this protective arrangement during wafer probe testing is an undesirable complication and expense in a circuit fabrication sequence. The present invention apparatus and method provide a viable alternative for this undesirable prior arrangement.
The patent art reveals a number of inventions which are of background and general interest with respect to the present invention. Included in this patent art is the U.S. Pat. No. 4,965,218 of A. E. Geissberger et al, which is concerned with a self-aligning gate arrangement in an integrated circuit. An interesting aspect of the Geissberger et al patent with respect to the present invention appears in column 5, line 31 where use of silicon nitride or other dielectric material as a passivation layer is described. In this use the passivation is applied over a single surface gallium arsenide wafer during a circuit fabrication sequence.
As is indicated at column 6, line 31 of the Geissberger et al patent, the silicon nitride passivation layer is also removed during a later part of the circuit fabrication sequence. The Geissberger et al patent also speaks at column 9, line 36 of using a dielectric encapsulant layer in order to protect the gallium arsenide wafer from a disassociation--wherein arsenic vaporization may occur as a result of high-temperature annealing. The Geissberger et al encapsulant material is said to be "possibly silicon nitride" at column 9, line 52 of the patent. The Geissberger et al patent also mentions the use of dielectric encapsulants of silicon nitride or silicon oxynitride materials at a number of other locations including column 20, line 50, column 21, line 7, and column 22, lines 55+. The latter location also mentions use of contact vias passing through the dielectric material. Although the Geissberger et al patent discloses the use of a silicon nitride layer on a gallium arsenide substrate, the location, accomplished function, and other aspects of this layer differ significantly from the arrangement of the present invention.
The patent art of interest also includes U.S. Pat. No. 4,849,376 issued to M. L. Balzan and E. E. Geissberger et al. The Balzan and Geissberger et al patent appears to use silicon nitride materials in combination with a gallium arsenide wafer for the same dielectric and encapsulation purposes employed in the above described Geissberger et al patent. Specific references to the use of silicon nitride layers in combination with a gallium arsenide wafer appear in the Balzan and Geissberger et al patent at column 5, line 20, column 5, line 65, column 6, line 18, column 9, line 37, and with several references to the silicon oxynitride material appearing in column 13 and in column 20 at line 48. As in the case of the Geissberger et al patent, the location and function of the layers taught in the Balzan/Geissberger et al patent and other differences distinguish the Balzan/Geissberger et al patent from the present invention.
This art also includes the U.S. Pat. No. 4,789,645 of J. A. Calviello et al, which is concerned with a top-down single furnace process for fabricating a microwave monolithic integrated circuit--a circuit of a type wherein active devices are later bonded to the passive microwave monolithic integrated circuit formed during the top-down processing steps. The Calviello et al patent also contemplates the use of a silicon dioxide layer to reduce crystal damage during the sputtering of silicon dioxide and silicon nitride dielectric layers. Such layers act as passivating films and in the capacity of improving isolation between circuits and N and N+ layers in the structure (see column 7, lines 44-54). The Calviello et al patent also indicates the use of silicon nitride material for dielectric purposes at column 3, line 45 and column 4, line 49. The location and function of silicon nitride layers and even the related material layers in the Calviello et al structure differ significantly from that of the present invention.
The patent art of interest also includes U.S. Pat. No. 4,972,250 issued to M. Omori et al, a patent concerned with protective coating or passivation layers employed during (or as a final step in) the fabrication of an integrated circuit die. It is notable that the Omori et al patent teaches against the use of materials such as silicon dioxide and silicon nitride overlaying gold and in lieu thereof espouses the use of diamond-like carbon material dispersed in a relatively thin layer over the top of an integrated circuit array. Both location of the film layer in the Omori et al patent and its passivation function differ significantly from teachings of the present invention.
This patent art also includes U.S. Pat. No. 4,977,100 issued to T. Shimura which is concerned with the fabrication of a MESFET--a MESFET used in a monolithic microwave integrated circuit. The Shimura patent speaks of three hundred angstrom thick films of silicon dioxide used during the fabrication process and of refractory metal materials such as tungsten silicon nitride used for gate electrode fabrication. The teachings of the Shimura patent are also readily distinguishable from the present invention, however.